The present invention relates to a solid-state image sensing apparatus which employs as image sensing elements static induction transistors, which have a versatility that enables them to serve as photoelectric transducers, amplifying elements and switching elements.
Conventional solid-state image sensing apparatuses which are widely utilized employ charge-transfer devices such as charge-coupled devices (CCDs) or MOS transistors. Such conventional image sensing apparatuses, however, suffer from the following problems: charges may undesirably leak out when they are transferred; the light-detecting sensitivity is disadvantageously low; and it is not possible for the degree of integration to be increased.
Novel solid-state image sensing apparatuses employing static induction transistors (referred to simply as "SITs", hereinafter) have been proposed to overcome the above-described problems. For example, the specification of Japanese Patent Laid-Open No. 15229/1980 discloses a solid-state image sensing apparatus in which SITs are arranged in a matrix, and the source, drain and gate of each of the SITs are, respectively, connected to a row line, a column line and a clear line.
Another type of conventional solid-state image sensing apparatus employs normally-OFF type SITs which are OFF when the gate bias is zero. This type of image sensing apparatus advantageously makes it possible to obtain a spike-shaped signal with a large amplitude since a signal is read within the charge injecting region. However, in this apparatus, the practically available range of SIT gate potentials at the time of reading is inconveniently narrow, that is, from the positive pinchoff voltage at which an SIT starts to turn ON to the gate voltage at which the injection of charges takes place from the gate to the source, which fact involves a disadvantageously narrow range of handleable quantities of incident light. In consequence, the amount of saturation exposure is unfavorably small.
In order to solve such a problem, a solid-state image sensing apparatus has been developed which employs normally-ON type SITs, which are ON when the gate bias is zero. FIG. 1(A) is a sectional view of an SIT which constitutes one picture element in a solid-state image sensing apparatus which employs normally-ON type SITs, the apparatus being disclosed in the specification of Japanese patent application No. 165237/1983 (Japanese Patent Laid-Open No. 58781/1985) previously submitted to the Japanese Patent Office by the applicant of the present invention and in the specification of U.S. Pat. No. 4,556,909 previously submitted to the Patent and Trademark Office of the U.S. Department of Commerce by yamada and assigned to the same assignee. FIG. 1(B) shows the general circuit configuration of one embodiment of the prior art apparatus, and FIG. 1(C) is a waveform chart of signals employed to operate the apparatus shown in FIG. 1(B).
As shown in FIG. 1(A), an SIT includes an n.sup.+ silicon substrate 1 which constitutes a drain. An n.sup.- silicon epitaxial layer 2 with a low impurity density is grown on the substrate 1. Then, an n.sup.+ source region 3 and p.sup.+ gate regions 4, 4 are formed on the surface of the epitaxial layer 2 by thermal diffusion or other similar method. An insulator film 5 such as SiO.sub.2 is deposited on each gate region 4, and a gate electrode 6 is deposited on the insulator film 5, whereby a capacitor 7 is formed by the insulator film 5 and the gate electrode 6. A reference numeral 8 denotes a gate terminal which is connected to both the gate electrodes 6, 6. The numeral 9 represents an isolation region made of, for example, a buried insulator, by which unit SITs respectively constituting picture elements are isolated from each other. The n.sup.- epitaxial layer 2 constitutes the channel region of the SIT. Since the SIT is of the normally-ON type, it is possible for the distance W.sub.g between the gate regions 4, 4 to be made relatively large. It is to be noted that it is also possible for the region 9 which isolates the picture elements to be formed by employing, for example, an n-diffused layer in place of an insulator.
As shown in FIG. 1(B), the solid-state image sensing apparatus is arranged such that normally-ON type SIT 20.sub.-11, 20.sub.-12, . . . 20.sub.-mn, each of which has the above-described construction, are arranged in a matrix, and signals are read by the X-Y addressing method. More specifically, the drain of each SIT which constitutes one picture element is grounded, and the respective gate terminals of the SITs disposed along lines which extend in the X-axis direction are connected to respective row lines 21.sub.-1, 21.sub.-2, . . . 21.sub.-m. On the other hand, the respective sources of the SITs disposed along lines which extend in the Y-axis direction are connected to respective column lines 22.sub.-1, 22.sub.-2, . . . 22.sub.-n, which are commonly connected to a video line 24 through respective transistors 23.sub.-1, 23.sub.-2, . . . 23.sub.-n for column selection. A video voltage V.sub.S is applied to the video line 24 through a load resistor 25.
The row lines 21.sub.-1, 21.sub.-2, . . . 21.sub.-m are connected to a vertical scanning circuit 26 such that signals .phi..sub.G1, .phi..sub.G2, . . . .phi..sub.Gm are respectively applied to these row lines. On the other hand, the respective gate terminals of the column selecting transistors 23.sub.-1, 23.sub.-2, . . . 23.sub.-n are connected to a horizontal scanning circuit 27 such that signals .phi..sub.S1, .phi..sub.S2, . . . .phi..sub.Sn are respectively applied to these gate terminals.
The following is a description of the vertical scanning signal .phi..sub.G and the horizontal scanning signal .phi..sub.S on the basis of the waveform chart shown in FIG. 1(C). Each of the signals .phi..sub.G1, .phi..sub.G2, . . . includes a voltage V.sub..phi.G having a relatively small amplitude and a voltage V.sub..phi.R having a larger amplitude than the former and is set such that the signal .phi..sub.G takes the value of V.sub..phi.G during a horizontal scanning period t.sub.H for one row line and takes the value of V.sub..phi.R during a blanking period t.sub.BL, that is, a period of time from the completion of horizontal scanning of one row line to the starting of horizontal scanning of the next row line. The horizontal scanning signals .phi..sub.S1, .phi..sub.S2, . . . which are applied to the respective gate terminals of the column selecting transistors are signals employed to select the corresponding column lines. The low level of the signals is set at a voltage value at which the column selecting transistors are turned OFF, while the high level of the signals is set at a voltage value at which these transistors are turned ON.
FIG. 2 is a circuit diagram of one picture element for describing the operation of each picture element. The reference numeral 20 denotes a normally-ON type SIT which comprises a grounded drain 1, a gate 4, a capacitor 7 formed between the gate 4 and a gate terminal 8, and a source 3. The gate 4 and the drain 1 of the SIT in combination form a p-n junction diode D.sub.G, as shown by the dotted line. The voltage-current characteristic of the diode D.sub.G, that is, the relationship between the gate potential V.sub.G and the gate-drain current I.sub.G, is such as that shown in FIG. 3(A). When the voltage across the diode D.sub.G, that is, V.sub.G, exceeds the built-in barrier voltage .phi..sub.B of the p-n junction, a forward currrent flows. The current I.sub.D flowing between the source and drain of the SIT is determined in accordance with the gate voltage V.sub.G. In a typical normally-ON type SIT, I.sub.D is proportional to the exponential function of V.sub.G and hence shows a characteristic curve such as that shown in FIG. 3(B).
Changes in the gate potential which take place when the signal .phi..sub.G is applied through the capacitor 7 to the gate 4 of the SIT shown in FIG. 2 will now be explained with reference to FIG. 4. When the signal .phi..sub.G becomes V.sub..phi.R at a time t.sub.1, the capacitor 7 is rapidly charged up to a voltage (V.sub..phi.R -.phi..sub.B). In consequence, the gate voltage V.sub.G becomes equal to .phi..sub.B. Then, when the signal .phi..sub.G becomes 0 V at a time t.sub.2, the diode D.sub.G is reverse-biased and, therefore, no current I.sub.G flows. In consequence, the voltage (V.sub..phi.R -.phi..sub.B) is
maintained across the capacitor 7, and V.sub.G =-V.sub..phi.R +.phi..sub.B. Thereafter, the charge Q.sub.L is accumulated by irradiation with light until a time t.sub.3 at which the signal .phi..sub.G is raised to V.sub..phi.G, and consequently, V.sub.G rises by .DELTA.V.sub.G =Q.sub.L /C.sub.G to become equal to -V.sub..phi.R +.phi..sub.B +.DELTA.V.sub.G.
When V.sub..phi.R at the time t.sub.3, the gate voltage V.sub.G rises to equal -V.sub..phi.R +.phi..sub.B +.DELTA.V.sub.G +V.sub..phi.G. If, at this time, the column selecting transistor 23 is turned ON in response to the signal .phi..sub.S, a current I.sub.D1 such as that shown in FIG. 3(B) flows through the SIT. This current I.sub.D1 causes a voltage drop V=I.sub.D1 .multidot.R.sub.L is generated on the video line 24. Since current I.sub.D1 changes with .DELTA.V.sub.G, it is possible for a signal corresponding to the quantity of incident light to be read out.
In FIG. 4, when the signal .phi..sub.G becomes V.sub..phi.R again at a time t.sub.4, the gate potential V.sub.G becomes .phi..sub.B. In consequence, the charge Q.sub.L accumulated so far is cleared. When the signal .phi..sub.G becomes 0 V at a time t.sub.5, the gate potential V.sub.G is reset at V.sub.G =-V.sub..phi.R +.phi..sub.B again, and the accumulation of charge for the next field is started.
As will be understood from the above description, the value of the voltage V.sub..phi.R of the signal .phi..sub.G which has a relatively large amplitude is selected such as to satisfy V.sub..phi.G &lt;V.sub..phi.R -.DELTA.V.sub.G from the condition that the gate potential at the time t.sub.3, namely, V.sub.G =-V.sub..phi.R +.phi..sub.B +.phi.V.sub.G +V.sub..phi.G, is smaller than .phi..sub.B, that is, -V.sub..phi.R +.phi..sub.B +.DELTA.V.sub.G +V.sub..phi.G &lt;.phi..sub.B, so that no gate current flows at the time of row selection.
The operation of the solid-state image sensing apparatus shown in FIG. 1(B) will next be explained on the basis of the operational principle of one picture element described above. When the signal .phi..sub.G1 becomes V.sub..phi.G in response to the operation of the vertical scanning circuit 26, the SITs connected to the row line 21.sub.-1 are selected, and as the column selecting transistors 23.sub.-1, 23.sub.-2, . . . 23.sub.-n are successively turned ON by the respective signals .phi..sub.S1, .phi..sub.S2, . . . .phi..sub.Sn which are output from the horizontal scanning circuit 27, optical signals are successively output from the SITs 20.sub.-11, 20.sub.-12, . . . 20.sub.-1n through the video line 24. Then, these SITs are reset when the signal .phi..sub.G1 becomes the high level V.sub..phi.R.
Then, when the signal .phi..sub.G2 becomes V.sub..phi.G, the SITs which are connected to the second row line 21.sub.-2 are selected, and optical signals are successively read out from the SITs 20.sub.-21, 20.sub.-22, . . . 20.sub.2n in response to the horizontal scanning signals .phi..sub.S1, .phi..sub.S2, . . . .phi..sub.Sn. Then, these SITs are reset. Thereafter, optical signals are successively read out from the respective picture elements in a similar manner to the above, and a video signal for one field is thereby obtained.
It has been confirmed as the result of experiments that the above-described operation proceeds smoothly. In the arrangement shown in FIG. 1(A), if the distance l.sub.GD between each gate region 4 and the drain 1 is large, the gate-drain current becomes correspondingly small owing to the resistance of the epitaxial layer 2, so that the gate potential may be incompletely reset. For this reason, the distance l.sub.GD is preferably set at a relatively small value, such as 1 to 3 .mu.m, from the characteristic point of view. The blanking period t.sub.BL is approximately 12 .mu.s in the case of the NTSC standard television system, and it is possible for the gate potential to be adequately reset within this period under the above-described condition.
The above-described embodiment of the prior art apparatus, which is disclosed in the aforementioned patent application, is effectively applied to a television camera which continuously picks up images. The above-described application for patent discloses another embodiment which may be suitably employed for a so-called electronic camera which picks up images frame by frame.
FIG. 5(A) shows the circuit configuration of the second embodiment of the prior art apparatus, while FIG. 5(B) is a signal waveform chart employed to describe the operation thereof. The fundamental arrangement of this embodiment is the same as that of the embodiment shown in FIG. 1(B). However, the former slightly differs from the latter in that the commonly connected drains 1 of the SITs 20.sub.-11, 20.sub.-12, . . . 20.sub.-mn, which constitute respective picture elements, are connected to a reset circuit 40 such that a reset signal .phi..sub.R is applied to the drain 1 of each SIT.
In FIG. 5(B), the reference symbol .phi..sub.R represents a reset signal which is applied to the drain 1 of each SIT. The reset signal .phi..sub.R becomes a negative voltage (-V.sub.R) only during a period when it resets the gate potential of each SIT, and takes 0 V during the other period. The vertical scanning signals .phi..sub.G1, .phi..sub.G2, . . . are raised to a high level V.sub..phi.G only during a period when the corresponding row lines 21.sub.-1, 21.sub.-2, . . . are scanned, and takes 0 V in the other period. The horizontal scanning signals .phi..sub.S1, .phi..sub.S2, . . . effect column selection. The reference symbol SH represents the opening and closing operation of a shutter which is provided on an electronic camera, while the symbol V.sub.G is a chart which shows changes in the gate potential.
The operation of this prior art apparatus will be described hereinunder on the basis of the waveform chart shown in FIG. 5(B). When the reset signal .phi..sub.R becomes a negative voltage (-V.sub.R) at a time tl, current flows between the gates and drains of all the SITs, and the gate potential V.sub.G is thereby reset at -V.sub.R +.phi..sub.B. Thereafter, the shutter is opened at a time t.sub.2 so as to allow irradiation with light.
Thus, the gate potential V.sub.G rises to 31 V.sub.R +.phi..sub.B +.DELTA.V.sub.G. Then, the vertical scanning signal .phi..sub.G1 becomes a high level V.sub..phi.G at a time t.sub.3. In consequence, the gate potential V.sub.G of the SITs connected to the row line 21.sub.-1 rises to -V.sub.R +.phi..sub.B +.phi.V.sub.G +V.sub..phi.G, and as the columns selecting transistors are turned ON in response to the horizontal scanning signals .phi..sub.S1, .phi..sub.S2, .phi..sub.Sn, signals are successively read out from the respective SITs 20.sub.-11, 20.sub.-12, . . . 20.sub.-1n.
Then, at a time t.sub.4, the signal .phi..sub.G1 is changed from V.sub..phi.G to 0 V and the signal .phi..sub.G2 is raised to the high level V.sub..phi.G, whereby signals are successively read out from the respective SITs 20.sub.-21, 20.sub.-22, . . . . Thereafter, signals are respectively read out from the SITs 20.sub.-31, 20.sub.-32, . . . 20.sub.-mn in a similar manner to the above, thus obtaining a video signal for one frame. When the reset signal .phi..sub.R becomes a negative voltage (-V.sub.R) at a time t.sub.5, current flows between the gates and drains of all the SITs. In consequence, all the gate potentials V.sub.G which have been raised by the irradiation with light are reset at -V.sub.R +.phi..sub.B, whereby it becomes possible to effect light exposure for the next frame.
FIG. 6(A) shows an arrangement obtained by partially modifying the embodiment of the prior art solid-state image sensing apparatus shown in FIG. 1(B). The circuit for operating each SIT shown in FIG. 1(B) employs the so-called grounded drain arrangement in which the drain is grounded and a positive voltage is applied to the source to read out the output, in a manner similar to that of the second embodiment described above. However, the prior art apparatus shown in FIG. 6(A) employs the so-called source-follower arrangement in which a positive voltage is applied to the drain and the source is grounded through a load resistance.
In this case, since a positive voltage is applied to the drain side, it is necessary in order to reset the gate potential to respectively provide reset transistors 50.sub.-1, 50.sub.-2, . . . 50.sub.-n for the column lines 22.sub.-1, 22.sub.-2, . . . 22.sub.-n to which the respective sources of the SITs are connected for the purpose of grounding these column lines. The reference numeral 51 denotes a reset control circuit which delivers reset pulses to the respective gates of the above-described reset transistors. The respective drains of the picture elements are connected in common on the substrate, and a positive drain voltage V.sub.D is applied to the drains.
Selecting scanning signals .phi..sub.G1, .phi..sub.G2, . . . and .phi..sub.S1, .phi..sub.S2, which are respectively applied to the row and column lines are similar to those in the prior art apparatus shown in FIG. 1(C) and are shown in FIG. 6(B). The arrangement differs from that shown in FIG. 1(C) only in that, prior to the application of a voltage with an amplitude V.sub..phi.R at the time tl when the row selecting signals .phi..sub.G1, .phi..sub.G2, . . . are reset, the reset transistors 50.sub.-1, 50.sub.-2, . . . 50.sub.-n having their drains respectively connected to the column lines 22.sub.-1, 22.sub.-2, . . . are turned ON in response to the reset pulse .phi..sub.R, thus causing the column lines to be grounded. At the reset time t.sub.1, all the sources of the SITs on all the column lines which are connected to a selected row line come to the ground potential, and the potential V.sub..phi.R is applied to the gates of the SITS. In consequence, a forward current flows to the ground through the column lines and the reset transistors, thus causing the gate potential to be reset. Changes in the gate potential are shown in FIG. 6(C).
In the prior art apparatus shown in FIG. 1(B), the gate potential is reset by means of a forward current which flows from the gate toward the grounded drain of each SIT. On the other hand, in this prior art apparatus the gate potential is reset by means of a forward current which flows from the gate toward the source connected to each of the column lines 22.sub.-1, 22.sub.-2, . . . which are grounded through the respective reset transistors 50.sub.-1, 50.sub.-2, . . . . The operation of this prior art apparatus with respect to the other points is completely the same as that of the first-described prior art apparatus.
In this prior art apparatus, if the voltage drop between the drain and source of each of the reset transistors 50.sub.-1, 50.sub.-2, . . . is large at the time of resetting the gate potential, the time required for the gate potential to be reset is increased correspondingly. It is therefore necessary to minimize the ON resistance of the reset transistors. For this purpose, it is necessary for each reset transistor to possess an adequately large gate width to gate length ratio.
As has been described above, the solid-state image sensing apparatus which has previously been disclosed by the applicant of the present invention has various advantages. However, in this apparatus the output of each picture element includes an offset or dark output as in the case of conventional solid-state image sensing apparatuses employing SITs. It is therefore necessary for these conventional solid-state image sensing apparatuses to cancel the offset or dark output. FIG. 7(A) shows the general circuit configuration of a conventional solid-state image sensing apparatus which employs SITs and is equipped with means for canceling the offset and dark output, while FIG. 7(B) is a signal waveform chart of the apparatus.
Referring to FIG. 7(A), the reference numeral 61 represents a solid-state image sensing apparatus having SIT image sensing elements 62. The apparatus 61 comprises light-shielded picture elements 63 on the first bit line, a vertical scanning circuit 64, column selecting transistors 65, a horizontal scanning circuit 66, a video line 67, a load resistor 68 and a video power supply 69. Since functional members which constitute each of the circuits are similar to those in the above-described embodiments of the prior art apparatus, description thereof is omitted.
The reference numeral 70 denotes a changeover switch which is connected to the video line 67. The switch 70 effects a changeover operation such that the offset or dark output included in the video output V.sub.1 shown in FIG. 7(B) is held in a sample-and-hold circuit 71. More specifically, the switch 70 effects a changeover operation in such a manner that the output of each of the light-shielded picture elements on the first bit line is held in the sample-and-hold circuit 71 for a horizontal scanning period t.sub.H, and the video output of the second bit line and those of the bit lines subsequent thereto are delivered to a differential amplifier circuit 72. The circuit 72 is fed with the light-shielded picture element output and the video outputs of the second bit line and the lines subsequent thereto and outputs a signal representing the difference therebetween. The video output V.sub.2 shown in FIG. 7(B) represents picture element outputs from the differential amplifier circuit 72 which delivers them after canceling any offset and dark output.
The above-described solid-state image sensing apparatus, however, has the following disadvantage. For example, in a state wherein the ambient temperature is relatively high, or in a state wherein the apparatus is provided with a shutter function and wherein the ambience is relatively dark and the time required for integration is consequently increased, the dark output is increased correspondingly, and hence, the dynamic range (the saturation output--the dark output) is undesirably decreased.